The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which may effectively be applied to a semiconductor integrated circuit device having field-effect transistors.
As semiconductor integrated circuit device having a storage function, a semiconductor integrated circuit device having a dynamic random-access memory (hereinafter abbreviated as a "DRAM") is known. Each of the memory cells in the DRAM is constituted by a series circuit consisting of a switching MISFET and a data storage capacitance element which are connected in series. The memory cells are respectively disposed at the intersections between word lines and data lines and are electrically connected to the corresponding word and data lines.
In one type of DRAM which adopts the folded bit line system, data lines are defined by a layer which extends above word lines. The word lines are defined by the same conductor layer as the gate electrodes of the switching MISFETs, for example, a polycrystalline silicon film. The data lines are formed from, for example, an aluminum film having an extremely small resistivity.
This type of DRAM however needs an unfavorably large area for connection between the memory cells (the source or drain regions of the switching MISFETs) and the data lines, and this disadvantageously prevents an increase in the scale of integration of the device. The area required for connection between the memory cells and the data lines mainly includes the area actually consumed for connection between these elements and the following various kinds of area: a margin of area needed to be left for mask alignment in the process for producing the memory cells and the data lines; an area needed to ensure the required dielectric strength of the region between the gate electrodes of the switching MISFETs and the data lines; and an area which is sufficiently large to prevent any damage to a field insulator film (isolation region) which defines the configuration of the switching MISFETs during formation of contact holes for connection between the memory cells and the data lines.
In view of the above-described circumstances, there has been devised a technique (self-aligned contact technique) with which data lines which are connected to the source or drain regions of MISFETs (memory cells) in a DRAM are self-aligned with respect to the gate electrodes of the MISFETs. This technique is described in the May 25, 1981, issue of "Nikkei Electronics", p. 132.